Teradyne posted its largest quarter ever in Q1 2026. Revenue grew 87% year over year. EPS blew past consensus. The CEO said roughly 70% of the quarter’s revenue was tied to AI demand. Look at the numbers and Teradyne reads like a textbook AI infrastructure beneficiary.

The stock did the opposite. After the print, shares dropped about 8.7% in after-hours trading. Including the regular session decline, a heavy wave of selling hit the name in a single day.

What happened?

Was the market less interested in the good Q1 number than in the slope of the next one.

This piece works through why Teradyne fell, and whether this company should be viewed as a plain ATE cycle stock, or as a test layer that becomes more important the more complex AI infrastructure gets.

Disclaimer

This article is for informational and analytical purposes. It is not a recommendation to buy or sell any specific security. All investment decisions are the reader’s own responsibility.

Table of contents

1. Why an 8% drop on a record print

2. What Teradyne actually does

3. One-time burst, or structural bottleneck

4. When testing one AI accelerator becomes an insurance premium

5. The HBM4 wafer sort win and a turning point for the memory business

6. Wafer to data center stack: from ATE company to test infrastructure company

7. Conclusion and watch list

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1. Why an 8% drop on a record print

Teradyne reported its largest quarter ever on April 28. Q1 2026 revenue came in at $1.282B, up 87% year over year. Non-GAAP EPS hit $2.56, beating the $2.11 consensus by 21%. In the press release, CEO Greg Smith said about 70% of the quarter’s revenue was linked to AI demand.

By the numbers it was hard to find a flaw. The market reaction said the opposite. After the print Teradyne fell about 8.7% in the after-hours session. Combined with the 5.4% drop already booked in the regular session, the one-day selling pressure was significant.

The reason isn’t that Q1 was bad. Q1 was too good. The problem is what comes next.

Teradyne guided Q2 revenue to a range of $1.15B to $1.25B. Midpoint is roughly $1.2B. In absolute terms, still very strong. Year over year, that’s 75%-plus growth. In the ATE industry, that kind of growth rate isn’t common.

But the market wasn’t looking at the absolute number. It was looking at the direction. Q1 revenue was $1.282B. Q2 guidance midpoint is $1.2B. Translated into plain English, the company essentially said, “Next quarter is still good, but it could be lower than this one.” That’s a sequential decline. Year over year still high growth, but quarter over quarter the line is bending down.

In a normal setup that’s not a big deal. But Teradyne had already run hard on AI test optimism. The stock was up more than 400% over the past year and had nearly doubled YTD. When a name has already moved that much, the bar shifts. Good earnings aren’t enough. The market also wants confidence that the next quarter will be better. The Q2 guide didn’t deliver that confidence.

Then OpenAI added fuel. The same day, the WSJ reported that OpenAI was missing its revenue targets. SoftBank fell nearly 10% in Tokyo. Oracle, CoreWeave, AMD, Nvidia, basically the entire AI infra basket, traded heavy. The market started asking the question again. Can the AI capex spent so far actually convert into revenue and profit.

Teradyne’s drop was the overlap of those two things. The Q1 numbers themselves were strong. The Q2 guide created the worry that “this quarter might have been the short-term peak,” and the OpenAI news scaled that worry up to AI infrastructure as a whole.

So what the market was selling wasn’t Q1. It was uncertainty about H2.

Now the real question is one thing. Is this drop a simple valuation reset on a stock that ran too far, or is it a signal that the AI test cycle is actually approaching peak. To answer that, you have to stop looking at Teradyne as just an ATE equipment maker, and start looking at it as the test layer that AI infrastructure has to pass through.

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2. What Teradyne actually does

A semiconductor can’t be sold the moment it leaves the fab. Each die on the wafer has to be checked. After packaging, it has to be checked again. If it’s an advanced package with HBM bonded to a logic die, the assembled package has to be verified. AI accelerators with high power and heat get one more round of validation under conditions closer to the real system.

The equipment that runs this work is ATE. ATE stands for Automated Test Equipment, the gear that pushes signals into a chip and automatically verifies that the expected response comes back.

Testing happens at multiple stages. Wafer probe is the step that checks each die on the wafer before it’s diced. A die is the individual chip cut from the wafer. Final test is the step that checks the chip after packaging. SLT, or System Level Test, runs the chip on a board or in a system, under conditions close to real operation.

In the past, wafer probe and final test could catch most issues. With AI accelerators the story shifts. Dies are getting bigger. HBM is bonded on top. High-speed I/O lanes multiply. Power and heat climb. Some failures don’t show up at the chip-level test. They only appear once the chip is on a board, running something close to a real workload. That’s why SLT is becoming more important.

Look at Teradyne’s revenue mix and you can see this shift in the numbers. Of Q1 2026’s $1.282B revenue, Semiconductor Test was $1.111B, or 87% of the total. In the past, mobile SoC test was a major leg of the business. Today, the center of gravity is moving to AI accelerator SoCs and HBM memory. In Q4 2025, SoC test revenue was $647M, up 47% sequentially. Memory test revenue was $206M, up 61% sequentially, an all-time quarterly high. For full-year 2025, the Compute category grew 90% year over year and became the largest contributor.

Teradyne’s core platforms map to this trend. UltraFLEXplus is used for high-performance SoCs and AI accelerator test. The Magnum series handles high-bandwidth memory test like HBM. SLT solutions sit on top of these, extending coverage from the chip level into system-level verification.

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3. One-time burst, or structural bottleneck

The question narrows to one thing.

Are Teradyne’s recent numbers a temporary burst from AI capex landing all at once, or are they structural test demand that has to keep growing as AI chips get bigger, more expensive, and more complex.

The difference matters. If the answer is the first one, Teradyne is a textbook cycle stock. Customers pile in tools for a stretch, then enter a digestion phase, and revenue rolls over. The market reacted strongly to the Q2 guide for exactly this reason. With the stock already up sharply, the doubt crept in: “Was Q1 the peak.”

If the answer is the second one, the story is different. As AI infrastructure grows, test stops being a cost line that gets squeezed and becomes a more important bottleneck. The more expensive a GPU gets, the taller the HBM stack, the more complex the package, the more high-speed I/O lanes there are, the higher the cost of catching a failure late. Customers end up testing at more steps, in conditions closer to real operation, and for longer.

From here, this article works through that question. Why some customers are starting to view 100% SLT as the cheapest option. Why HBM4 is creating new test insertions. And why Teradyne’s moves over the last 13 months point in the same direction.

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On the morning of April 7, Intel posted a single line on X. “Intel is proud to join the Terafab project with SpaceX, xAI, and Tesla to help refactor silicon fab technology.”

It was a strangely quiet announcement.

No press release.

No SEC filing.

On the surface, it looks simple.

1. Intel joined Terafab, and the market liked it.

2. Intel could get Tesla volume, so the stock went up. End of story.

But this deal has too many weird angles for that kind of read.

SpaceX filed a confidential IPO with the SEC on April 1. The target valuation was reported at over $1.75 trillion, with a fundraising goal around $75 billion.

Meanwhile, Samsung had already locked in a $16.5 billion long-term AI6 chip supply contract with Tesla.

And then Intel slid into the middle.

What makes it more interesting is Intel’s own position. Intel Foundry posted $17.8 billion in revenue for 2025 but recorded $10.3 billion in operating losses, and external customer revenue was just $307 million.

Why would a company in that shape react so sharply to this deal?

Reading this as simply “good news for Intel” is one-dimensional.

Behind the surface announcement, a much bigger game is playing out.

Articles worth reading together:

Why Intel Foundry Is All-In on This Deal

According to Intel’s annual report, Intel Foundry’s external customer revenue in 2025 was $307 million. That is 1.7% of its total foundry revenue of $17.8 billion. The rest is essentially internal volume. Annual operating loss was $10.3 billion. With a structure like that, it is very hard to convince the market that the foundry can stand on its own without external customers. Whether it is a spinoff or an IPO, what the market ultimately wants to see is an answer to one question:

“Is this really a foundry that other companies would trust with their chips?”

So what Intel Foundry needs most right now is not a technology demo.

It needs customers. Not names on a slide, but anchor customers who commit volume over time and generate real revenue. Microsoft is already public as an Intel Foundry customer, and AWS announced a collaboration on custom AI chips based on Intel 18A in 2024. But those are still more symbolic than substantial. To genuinely shift the narrative for Intel Foundry, it needs large-scale, sustained external demand.

In that context, Terafab is not just another collaboration headline for Intel. It is the closest thing to the anchor customer that Intel so desperately needs right now. Of course, there are caveats. The information that has been made public so far amounts to a “joining” announcement. Key contract details like wafer volumes, capex sharing, and long-term capacity guarantees are nowhere to be seen.

The phrase in Intel’s post, “help refactor silicon fab technology,” suggests something deeper than simple wafer supply. But the fact that this was announced through a single X post with no press release or SEC filing also suggests this has not yet reached the stage of a formal contract.

So you should not read this as a confirmed order.

At this stage, Terafab is closer to a possibility than a contract.

So What Does Intel Actually Get Right Now?

If there is no formal contract yet, what does Intel actually gain from this deal? I see two things.

The first is credibility. This may not translate to revenue right away, but for Intel Foundry, credibility is what matters most at this moment. Under Lip-Bu Tan, Intel has been restructuring its manufacturing control and capital structure. On April 1, Intel repurchased a 49% stake in its Ireland Fab 34 from Apollo for $14.2 billion, regaining full control of the fab. Add CHIPS funding and government capital on top of that, and Intel has at least secured enough staying power along with the image of being a national strategic asset.

The technology side is not standing still either. The perception that “Intel is coming up faster than expected” has started to form in parts of the market, and it is at that exact moment that the Terafab name got attached. That sends a signal to both the market and Washington: “Intel has at least secured a seat at the table for the U.S. AI manufacturing hub.”

Here is my bigger read on this. The short-term value of Terafab is not about how many wafers Intel prints right away.

It is about repositioning Intel Foundry as

For a foundry starved of external customers, this alone can function as a qualification event. Real large-scale revenue is a later problem. What Intel needs first is a reason for other potential customers to take a second look. In that sense, Terafab is both a pipeline story and a sales story.

The second is packaging. This is far more tangible than credibility. If you only look at Terafab through the lens of process nodes, you miss the point. The area where Intel can contribute most immediately, and monetize most quickly, is likely advanced packaging.

Intel’s Foveros and EMIB are still considered top-tier capabilities in the industry. Meanwhile, the real bottleneck in the market has been showing up more often in advanced packaging than in the node itself. TSMC’s CoWoS being capacity-constrained is practically an open secret, and even Nvidia has dealt with shipment bottlenecks due to packaging capacity limits. What matters in the AI chip race right now is not just cutting transistors smaller. It is how you attach HBM, how you connect chiplets, how you manage power delivery and thermals. Those are the factors that determine real-world performance and shipment volumes. In that sense, Intel’s packaging capabilities are an asset that can convert to revenue faster than 18A itself.

So the short-term picture probably looks more like this. AI6 wafer production is already pointed at Samsung’s Taylor facility, and AI5 is reportedly going to TSMC. Intel enters initially through packaging services and process co-development. Rather than a sudden flood of external wafer revenue, the progression is more likely to start with advanced packaging and enablement, with logic wafer opportunities following after.

Reading this as Intel taking over Terafab’s manufacturing operations at this stage would be getting ahead of the story.

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In March 2026, Broadcom’s Natarajan Ramachandran stood in front of reporters and said something that would have been unthinkable a few years ago.

From unlimited to bottleneck. This shift happened in just two to three years, and it wasn’t an accident. Yes, the explosion in AI demand played a role. But if you understand the structure of this industry, you can see exactly why everything converges on TSMC, and why switching to another foundry is not simply a matter of picking up and moving.

The TSMC bottleneck is an opportunity for Samsung and Intel. That part is true.

What most people get wrong is what kind of opportunity it actually is.

There’s a significant gap between what the market expects and what’s actually happening on the ground, and understanding that gap is what separates a good investment thesis from a bad one. This piece starts with how fabless companies and foundries actually work together, then moves to why customers can’t leave TSMC, where Samsung and Intel can realistically make money, and what conditions would have to hold for this dynamic to break.

In this piece:

• How Chips Get Made: The Fabless-Foundry Relationship

• Why TSMC Is So Hard to Catch

• The Real Shape of the TSMC Bottleneck

• Samsung Foundry: Where Things Actually Stand

  • What We Know and What We’re Estimating

  • The Taylor Fab: A $44B Bet, Up Close

  • What I’m Hearing on the Ground

  • My Take (Speculation Warning)

• Intel Foundry: Where Things Actually Stand

  • What We Know and What We’re Estimating

  • Apple Is Coming Back to Intel

  • NVIDIA’s Feynman and Intel

  • The Risks Underneath the Good News

  • Where Intel Foundry Can Start Making Money: EMIB and “Made in USA”

• What Betting on the “Not TSMC” Market Actually Means

• Closing Thoughts

  ---

Disclaimer: All content in this article is based on my personal analysis of publicly available materials, press reports, analyst research, and industry networks. It is not based on any NDA-protected information from my current or former employers. This is not investment advice.

How Chips Get Made: The Fabless-Foundry Relationship

The most common misconception among investors new to semiconductors goes something like this:

“If TSMC is too expensive, why not just switch to Samsung or Intel?”

To answer that question, you first need to understand how a fabless company actually works with a foundry. The short answer is that switching foundries is not changing factories. It’s redesigning the chip from scratch.

Where Every Design Starts: The PDK

When a fabless company designs a chip, it does not start with a blank canvas. It starts on top of a PDK, or Process Design Kit, provided by the foundry.

Let me explain concretely what a PDK contains. Every foundry runs a different process. The physical characteristics of transistors differ, the number and thickness of metal interconnect layers differ, the minimum spacing between devices differs. The PDK packages all of those differences into a form that a design team can actually use. Specifically, it includes the following.

SPICE models are mathematical descriptions of how each individual transistor behaves electrically. When a designer runs circuit simulations, these models tell you: “At this foundry, on this process, if you apply 1V to this transistor, here’s how much current flows and here’s the switching speed.” Change the foundry, and the models change entirely. Draw the same circuit and you get a completely different set of electrical characteristics.

DRC, or Design Rule Check, rules are physical constraints. Things like “minimum spacing between these two metal lines: X nanometers,” or “minimum via size: Y nanometers.” There are thousands of these rules. Violate them and you get shorts or opens in manufacturing. Every foundry uses different equipment and different lithography approaches, so every foundry has a different set of rules.

LVS, or Layout vs. Schematic, verifies that the physical layout a designer drew actually matches the intended circuit. Standard cell libraries are pre-designed collections of basic digital building blocks, AND gates, OR gates, flip-flops, all optimized for the specific process characteristics of that foundry. Designers assemble chips by combining these cells like Lego bricks.

Put it together and the PDK is everything you need to know to design a chip on that foundry’s process. Design teams operate entirely within the PDK. Step outside it and the chip either cannot be manufactured or will not work when it is.

So if you spent two years designing a chip on TSMC’s PDK and want to move it to Samsung Foundry, you have to redesign it from scratch on Samsung’s PDK. Different SPICE models means all simulations get re-run. Different DRC rules means all layouts get redrawn. Different standard cells means synthesis has to be redone. It’s a new project, full stop.

DTCO: When Design and Process Get Tangled Together

There’s a more recent development that makes this even harder. It’s called DTCO, or Design-Technology Co-Optimization.

For a long time, the sequence was: foundry develops the process, creates a PDK to match, hands it to the fabless customer, and the customer designs from there. Through 7nm and 5nm, that workflow mostly held.

At 3nm, and especially below 2nm, that sequence broke down. The transistor architecture itself shifted from FinFET to GAA, or Gate-All-Around, nanosheet structures, and design freedom and process constraints became far more deeply intertwined. For example, a wider nanosheet channel carries more current but reduces device density. A narrower channel gives you better density but less performance. These kinds of tradeoffs now get decided jointly between the design team and the process team from the very beginning of a project.

Metal stack configuration is the same story. An AI accelerator burning enormous amounts of power needs thick metal layers for efficient power delivery. A mobile AP prioritizes thin layers to shrink area. These choices get locked in at the start of the process, not at the end.

The result is that at 2nm and below, the option to “switch foundries later” has become dramatically more constrained. The chip’s architecture gets shaped around a specific foundry’s process characteristics early in the design phase. Moving to another foundry later means unwinding far more than it ever did in previous generations.

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Tapeout: The $100M Decision You Cannot Take Back

When a design is complete, it goes through tapeout. The finished design data, in GDSII format, gets handed to the foundry, which uses it to manufacture photomasks, the plates used to print circuit patterns onto silicon wafers. Once a mask is made, it cannot be modified. Change the design and you need new masks.

Mask costs scale dramatically with each new node. By IBS estimates, a mask set at 28nm runs about $2M. At 7nm it’s $15M. At 5nm, $40 to $50M. At 3nm, over $100M. The raw mask count tells the story: roughly 40 masks at 28nm, over 80 at 7nm. The increase comes from EUV lithography and multi-patterning, where printing finer features requires more process steps and therefore more masks.

Before tapeout, a design has to pass DRC, LVS, simulation across process corners (fast, slow, typical), power integrity verification, and thermal analysis. And even then, first silicon rarely goes straight to volume production. Most designs go through one or two re-spins, each costing tens of millions of dollars.

When a single tapeout at 3nm costs over $100M in masks alone, saying “I don’t like this foundry, let’s switch” means “let’s write off everything we’ve invested in design and masks and start over.” That is the real texture of switching costs.

Dual-Vendor Strategy: What I Saw Firsthand at Qualcomm

The natural follow-up question is: Why not run both foundries simultaneously?

Companies do.

When I was at Qualcomm, we ran Samsung and TSMC at the same time.

But what that actually involves is not what most people imagine. It is not “get quotes from two foundries and go with the cheaper one.” The process starts two to three years before launch, with parallel design work on both PDKs. Separate design teams are assigned to each, running simulations to compare PPA, which stands for Power, Performance, and Area, across both processes. You want to know which process delivers better numbers, and how timing margins differ when you run the same design through each.

Then you fabricate test chips at both foundries independently. When those come back, you measure silicon performance. Which foundry shows better model-to-hardware correlation? What are the yields? How many chips fall outside spec at certain process corners? This characterization work runs over two to three years, and only after enough data accumulates do you decide how to split the volume.

The only companies that can do this are Qualcomm, Apple, NVIDIA, the large-scale fabless players. You need the engineering headcount to run parallel design programs on two PDKs for multiple years simultaneously. For a smaller fabless company, dual-sourcing is not a realistic option. Pick a foundry and you’re committed for two to three years.

TSMC’s OIP: Locking In the Entire Ecosystem

TSMC has a program called OIP, or Open Innovation Platform, that maximizes this lock-in. It integrates EDA vendors like Synopsys and Cadence, IP vendors like ARM, and TSMC’s own packaging technologies like CoWoS and SoIC into a unified reference flow.

Why is this so powerful? The EDA tools a fabless company uses to design a chip need to be validated against the foundry’s PDK. Whether you’re using Synopsys Fusion Compiler for synthesis or Cadence Innovus for place-and-route, it only works well if a validated flow for that foundry’s PDK exists. TSMC works closely with major EDA vendors to release PDK-optimized reference flows first. IP vendors validate and release their IP on TSMC processes first.

For a fabless company, designing on TSMC’s OIP means EDA compatibility, IP validation, and packaging integration all come as a bundle. Using a different foundry means verifying every piece of that stack separately. If a particular IP block hasn’t been validated on that process, you wait for the IP vendor to do it. Intel 18A ran into exactly this problem, where IP validation delays slowed customer adoption.

Moving a chip designed within TSMC’s ecosystem to another foundry requires redesign work, IP re-validation, EDA flow reconstruction, and full timing re-verification. Technically possible. Practically, almost nobody does it. Switching foundries is not switching factories. It’s switching design infrastructure entirely. Once you’re on a PDK, two to three years of investment is locked in. That’s the first reason TSMC is hard to catch.

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Why TSMC Is So Hard to Catch

PDK lock-in is only the starting point. TSMC’s moat is not a single wall. It’s layers stacked on layers.

The Yield Flywheel: Forty Years in Motion

Morris Chang established a strategy during his time at TI that he carried into TSMC: stay ahead of the cost curve. Price below current cost to win volume, use that volume to improve yield, let yield improvement drive cost down, use lower costs to attract more customers. A flywheel.

TSMC has been spinning that flywheel since its founding in 1987. As of Q3 2025, quarterly revenue was NT$989.92 billion (roughly $33.1B), up 30.3% year-over-year, with gross margin of 59.5% and operating margin of 50.6%. The 3nm node accounted for 23% of wafer revenue, 5nm 37%, and 7nm 14%. Advanced nodes below 7nm together represent 74% of total wafer revenue.

What those numbers tell you is simple. TSMC is the only foundry that can make money on advanced nodes and reinvest it into the next generation at the same time.

The Capex Gap: Three Times Over

TSMC’s annual capex for 2026 is estimated at $52 to $56 billion. Intel’s is $16 billion. TSMC is building more than three Intels every year. Samsung Foundry’s capex runs even lower.

On 3nm capacity alone, TSMC is targeting over 200,000 wafer starts per month by end of 2026, expanding toward 250,000 by 2027. Volume production on 2nm started at Fab 22 in Kaohsiung in Q4 2025, with additional phases under construction. In a capital-intensive industry, a capex gap is a capacity gap, and a capacity gap is a customer gap.

Advanced Packaging: The Second Moat

TSMC’s advanced packaging capabilities have emerged as another major competitive advantage. CoWoS capacity is projected to expand from roughly 35,000 panels per month at end of 2024 to between 110,000 and 125,000 by end of 2026, with some estimates reaching 170,000 by end of 2027. CoWoS-L, SoIC, and CoPoS slated for introduction after 2027 all point to TSMC maintaining its lead on the packaging roadmap as well.

By analyst estimates, NVIDIA holds over 60% of CoWoS-L capacity, and Apple has locked in more than half of early 2nm allocation. When you factor in packaging, the exits from TSMC’s ecosystem shrink to almost nothing.

The Trust Moat: The Only Foundry That Doesn’t Compete With Its Customers

There’s one more structural advantage embedded in TSMC’s business model. It’s a pure-play foundry. TSMC designs no chips of its own. It never competes with its customers.

Samsung is different. Samsung designs Exynos APs for its own Galaxy smartphones while simultaneously manufacturing Qualcomm’s Snapdragon. From a customer’s perspective, handing over critical IP to a direct competitor is a fundamentally uncomfortable arrangement. This structural conflict of interest is Samsung Foundry’s chronic trust problem.

Intel faces the same issue. An IDM running its own CPUs while offering to manufacture chips for outside customers invites the obvious concern: won’t Intel prioritize its own chips over mine?

Talent and Culture: The Things You Cannot Buy

Morris Chang once said that American semiconductor manufacturing is “a very expensive exercise in futility.” It sounds harsh, but it’s not wrong. Taiwan has over thirty years of accumulated manufacturing talent. Suppliers, universities, shift workers, every layer of the stack is precisely calibrated around a single mission: manufacturing the best chips in the world. You can build a fab with money. You cannot buy the knowledge that lives inside it.

There was substantial reporting on culture clashes at TSMC’s Arizona fab, where American engineers’ expectations around work-life balance ran headlong into the Taiwanese management culture of unconditional commitment. This is not just an HR problem. In manufacturing, culture becomes yield, and yield becomes money.

TSMC’s moat is not a single technology. It’s the yield flywheel, the scale, the ecosystem, the packaging, the trust, and the culture, all stacked on top of each other. Catching up on any one of them does not mean much on its own.

One is Samsung’s memory business.

Starting with HBM4, the base die at the bottom of the DRAM stack needs to be manufactured on an advanced foundry process. Samsung is the only company in the world that owns DRAM, logic foundry, and packaging all under one roof, and it is now actively turning that vertical integration into a foundry customer pitch.

The other is Intel’s EMIB.

With TSMC’s CoWoS in short supply, Intel’s advanced packaging technology is emerging as the only real alternative at scale. The reports that NVIDIA’s next-generation Feynman chip will use EMIB are a signal that the packaging competition is entering a new phase.

How these two variables are creating real opportunities for Samsung and Intel in the TSMC bottleneck era, drawing on what I’m hearing on the ground, is what the rest of this piece covers.

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If you had to name the single hottest keyword in the semiconductor industry right now, I’d say hybrid bonding without hesitation.

EUV lithography was the revolution that shrank transistors horizontally. Hybrid bonding is the revolution that stacks chips vertically. As transistor scaling approaches its physical limits, the path to higher performance is no longer about making chips smaller: it's about stacking multiple chips in three dimensions and making them behave as one. Hybrid bonding is the core technology that makes that 3D integration possible.

For this article, I conducted direct interviews with engineers currently working at Samsung, SK Hynix, and Micron. This piece covers what hybrid bonding is, how it differs across applications, why it's uniquely difficult for HBM, whether it will actually be adopted, and who the beneficiaries are.

Table of Contents

1. What Is Hybrid Bonding

2. Bonding Methods: W2W, D2W, and D2D

3. Where Hybrid Bonding Is Applied, and Why Some Are Harder Than Others

4. Why HBM Hybrid Bonding Is So Much Harder

5. Will HBM Actually Use Hybrid Bonding?

6. Beneficiary Analysis: Who Makes the Money

1. What Is Hybrid Bonding

The old way: bumps

The most traditional method for connecting chip to chip is the bump. A bump is a tiny solder ball that protrudes from the chip surface. You align the bumps on chip A with the bumps on chip B, apply heat and pressure, the solder melts, and the two chips form an electrical connection.

TCB (Thermo-Compression Bonding), currently the dominant method in HBM, works exactly this way. A filler material, either NCF (Non-Conductive Film) or MUF (Molded Underfill), is injected between chips to fill the gaps around the bumps. SK Hynix's MR-MUF (Mass Reflow Molded Underfill) is the best-in-class implementation of this approach.

The problem is that bumps take up space. If the bump pitch (center-to-center distance between bumps) is 40μm, there is an unavoidable gap of tens of microns between chips. That’s fine when you’re stacking four dies. When you need to stack 12, 16, or eventually 20, those accumulated gaps become a hard constraint on total package height.

Hybrid bonding: eliminate the bump

Hybrid bonding removes bumps entirely. Instead of a solder ball, the chip surface exposes bare copper pads surrounded by a dielectric (SiO₂ or SiCN). When two chips are pressed face-to-face, the dielectrics bond first at room temperature or low temperature. A subsequent annealing step heats the assembly, causing the copper pads to expand thermally and form a direct metal-to-metal bond.

Why “hybrid”?

Because dielectric bonding and metal bonding happen simultaneously. It’s not purely copper bonding, and it’s not purely dielectric bonding. The two mechanisms work in tandem.

What that actually means:

First, no bumps means virtually zero gap between chips. You can fit more dies within the same total height. Second, bump pitch was 40μm; with hybrid bonding it can drop below 10μm, and ultimately to sub-micron. Interconnect density goes up by orders of magnitude. Third, removing the bump as an intermediary lowers electrical resistance, speeds up signal transmission, and reduces power consumption. Fourth, bumps were a thermal bottleneck between chips; hybrid bonding also improves heat transfer across the die-to-die interface.

In short: hybrid bonding enables 3D stacking that is denser, faster, more interconnect-rich, and thermally superior.

Pitch: what it is, and why it matters

Earlier I said bump pitch goes from 40μm down to below 10μm. Here’s what that actually means.

Pitch is the center-to-center distance between adjacent connection points. Think of a grid: the spacing between intersections is the pitch. The tighter the spacing, the more connection points you can fit in a given area.

The numbers tell the story. At 40μm pitch, you can fit 25 connection points along a 1mm line. Extend that to a 1mm × 1mm area and you get roughly 625 total connections. At 10μm pitch? 100 per millimeter, 10,000 per square millimeter. Cut the pitch by 4x and interconnect density jumps 16x. Push hybrid bonding to 1μm pitch and you get one million connections per square millimeter — 1,600x the density of a 40μm bump.

Why does this matter for HBM? The HBM4 interface is 2,048 bits wide, double the 1,024 bits of HBM3E. Bit count is the number of “lanes” available to send and receive data simultaneously. More lanes means higher bandwidth. HBM4’s per-stack bandwidth of 2TB/s comes directly from that wider interface.

The challenge is fitting 2,048+ I/O pins into the physical footprint of an HBM die. The area is limited. At 40μm pitch, you simply cannot pack that many I/Os into the available space. HBM4 already requires pitch to be pushed well below 40μm, and future generations will need to approach 10μm. At that point, bump-based TC Bonding hits a wall — the physical size of the bump itself is the bottleneck.

Hybrid bonding solves this at the root. Copper pads sit flush with the chip surface rather than protruding, so the pads themselves can be made much smaller. Smaller pads mean tighter pitch, which means more I/Os in the same area. Below 10μm pitch, you can fit tens of thousands of connection points — more than enough to support 2,048 bits and beyond.

The chain of logic: tighter pitch → more connections per unit area → wider interface → higher bandwidth. HBM bandwidth requirements are growing explosively with each generation. The physical foundation for that bandwidth is pitch. Hybrid bonding is what breaks through the physical limits on pitch.

One more thing. Tighter pitch doesn’t just add connection density. Shorter interconnect paths reduce parasitic capacitance and inductance, which speeds up signal transmission and lowers power consumption. HBM4’s per-pin data rate of 8Gb/s is built on exactly these physical improvements.

The non-negotiable prerequisite: atomic-level surface flatness

For hybrid bonding to work, chip surfaces must be flat at the atomic scale. TC Bonding can tolerate surface irregularity because molten solder compensates for height variations. Hybrid bonding has no such buffer. Surface roughness must be on the order of a few angstroms (1Å = 0.1nm).

The process that achieves this flatness is CMP (Chemical Mechanical Planarization). CMP combines chemical reaction and physical polishing to bring copper pad height and surrounding dielectric height into alignment at the nanometer level. Applied Materials (AMAT) holds a dominant position in the CMP equipment market for hybrid bonding applications. Competitors like Japan’s EBARA exist, but AMAT’s technical lead in hybrid bonding-specific CMP is firmly established. The fact that the real gating factor in hybrid bonding is not the bonder itself but the upstream CMP process will come up again when we get to the beneficiary analysis.

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2. Bonding Methods: W2W, D2W, and D2D

Before getting into the Hybrid bonding applications, it helps to understand the three primary bonding methods. W2W, D2W, and D2D are not concepts unique to hybrid bonding; they apply to bonding broadly. But in practice, they come up far more often in the hybrid bonding context. The reason is that hybrid bonding is extremely sensitive to alignment error, particle contamination, and yield loss, which means the choice of assembly format has an outsized impact on both yield and cost.

The Three Methods: W2W, D2W, and D2D

W2W (Wafer-to-Wafer)

Two fully fabricated wafers are aligned and bonded face-to-face as complete units. Alignment and bonding occur in separate chambers, which is why this method delivers the highest alignment accuracy, throughput, and bond yield of the three.

The constraint is that both wafers must have identically sized dies, which rules out heterogeneous integration. And because entire wafers are bonded at once, there’s no opportunity to screen out defective dies beforehand. W2W works best for small, high-yield chips where the yield loss from bonding a bad die to a good one is manageable.

Applications: Sony CIS, YMTC Xtacking (3D NAND), Micro-LED microdisplays, 3D DRAM CBA.

D2W (Die-to-Wafer)

Individual dies are placed and bonded onto a target wafer. This enables KGD (Known Good Die) selection and allows dies of different sizes, thicknesses, and process nodes to be combined on a single wafer, making it the method of choice for heterogeneous integration. D2W splits into two distinct sub-approaches.

DP-D2W (Direct Placement D2W): Individual dies are picked, flipped, and placed directly onto the target wafer one at a time using a high-precision flip-chip bonder. Maximum flexibility for mixing different die types, but the lowest throughput of the D2W approaches. Each die requires individual surface cleaning and activation, which makes particle control a persistent challenge. Besi’s hybrid bonder is the leading equipment platform for this method.

Applications: HBM stacking (future generations), select TSMC SoIC configurations.

Co-D2W (Collective D2W): Individual dies are first placed onto a carrier wafer, then the carrier and target wafer are bonded together in a single W2W-like step. This improves throughput over DP-D2W and partially inherits W2W alignment advantages, but adds process steps for carrier preparation, temporary bonding, and carrier separation. EVG is the key equipment supplier for this approach.

Applications: Silicon photonics, TSMC SoIC (reconstituted method).

A notable variant here is Reconstituted W2W, used in TSMC’s SoIC platform. Dies for both the top and bottom layers are individually placed onto separate carrier wafers, and the two carriers are then bonded W2W. AMD’s 3D V-Cache is built this way. A single V-Cache chip requires five bond steps: bottom CPU die to carrier, V-Cache chiplet to carrier, two dummy silicon pieces to carrier, and finally wafer-on-wafer.

D2D (Die-to-Die)

An individual die is bonded directly onto another individual die without a wafer substrate. Complete flexibility, but the lowest throughput of the three methods and significant alignment challenges. Currently limited to research and prototyping. IBM demonstrated D2D hybrid bonding at 2.5μm pitch at IEDM 2024.

Applications: Research and prototype stage only.

With that framework in place, here’s how each major application maps onto these methods, and why some are dramatically harder than others.

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3. Where Hybrid Bonding Is Applied, and Why Some Are Harder Than Others

CMOS Image Sensors (CIS): where hybrid bonding was born

CIS was the first application to reach mass production with hybrid bonding. Sony’s IMX260, which shipped in the Samsung Galaxy S7 in 2016, was the first commercial product, built on Xperi’s (now Adeia) DBI (Direct Bond Interconnect) technology under license.

Hybrid bonding in CIS is relatively straightforward. The reason is simple: it uses wafer-to-wafer (W2W) bonding. The pixel array wafer and the signal processing logic wafer are bonded as complete wafers. Both wafers have matching chip sizes, and image sensors tend to have relatively high yields, making W2W viable. W2W bonds an entire wafer at once, which drives high throughput, and alignment precision of around 200nm is sufficient.

Key point: CIS is a two-layer stack. You bond two wafers. That’s it.

Logic/HPC (3D V-Cache, chiplets): the D2W domain

AMD’s 3D V-Cache is the defining example here. TSMC’s SoIC (System on Integrated Chip) platform is used to stack an SRAM cache die on top of a CPU die. Intel’s Foveros Direct falls in the same category.

These applications require die-to-wafer (D2W) bonding. Why not W2W? Because the two dies being bonded are different sizes.

The V-Cache die and the CPU die have different footprints. Combining chips of different dimensions requires placing individual dies onto a wafer one at a time.

D2W is technically much harder than W2W. Handling individual dies increases particulate contamination risk. The dicing process can introduce edge damage. Throughput is significantly lower than W2W.

The tradeoff is that D2W allows KGD (Known Good Die) selection, letting you screen out defective dies before bonding. With W2W, you bond entire wafers together, so a bad die on one side kills the good die it’s bonded to on the other.

Key point: Logic/HPC uses D2W, requires sub-10μm pitch, and demands alignment accuracy below 100nm. Typically two to three layers.

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The bottleneck in the semiconductor industry has shifted. For a long time, almost everything came down to how small you could make a transistor. That’s no longer the whole story. Increasingly, what matters is how fast and efficiently you can connect multiple chips inside a single package. Packaging has become a critical competitive axis.

The dominant technology in this space is TSMC’s CoWoS (Chip on Wafer on Substrate). NVIDIA’s AI GPUs, AMD’s accelerators, Broadcom’s custom ASICs — most high-performance AI chips today are packaged using CoWoS. The problem is supply can’t keep up with demand. By industry estimates, NVIDIA absorbs a substantial portion of available CoWoS capacity, leaving other customers struggling to secure allocation. This has been going on for a while now.

Into this gap steps Intel’s EMIB (Embedded Multi-die Interconnect Bridge). In March 2026, Intel CFO David Zinsner told the Morgan Stanley conference that the packaging business was shaping up to be significantly larger than originally anticipated. Multiple outlets reported that Intel’s EMIB was being evaluated for NVIDIA’s next-generation architecture.

This piece breaks down what EMIB is, how it differs from TSMC’s approach, and what it could mean for Intel Foundry.

Substack is currently in a trial phase, so all premium quality articles are available for free for now. Once paid subscriptions are introduced, pricing will be set at a level comparable to professional tech writers on Substack. Early supporters will have the benefit of locking in their current pledge price for future paid access.

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1. Why Advanced Packaging Suddenly Matters

Some context first.

AI-era chips can’t perform on their own. Take a single NVIDIA GPU: the logic die handling computation and the HBM (High Bandwidth Memory) storing data need to exchange information at extreme speeds inside one package. Advanced packaging is what makes that connection possible.

The old approach was monolithic design — pack everything into one large chip. But as chips get bigger, defect rates climb and costs spike. So the industry changed course. Instead of one large chip, you build multiple smaller chips (chiplets), each optimized for a specific function, and assemble them within a package. Think of it as LEGO blocks. The quality of the connections between those blocks determines total system performance.

2. CoWoS vs EMIB: Highway vs Bridge

There are several ways to connect chips inside a package. The two that matter most right now are TSMC’s CoWoS and Intel’s EMIB. To understand the difference, you need to understand interposers.

What Is an Interposer?

An interposer is essentially a middleman substrate placed between chips. You put a compute chip and a memory chip on top of this substrate and route data between them through extremely fine metal traces embedded in the substrate. Because the traces are much denser and shorter than what you’d find on a standard PCB, data moves faster and power consumption drops.

The question is what you make the interposer out of. Silicon enables extremely fine traces and delivers excellent performance, but silicon interposers are expensive. They’re fabricated on semiconductor wafers using processes similar to chip manufacturing itself. Larger interposers mean higher defect probability and sharply rising costs.

CoWoS: TSMC’s Approach

TSMC’s CoWoS places a large silicon slab beneath all the chips in the package, routing inter-chip communication through extremely fine traces embedded in that slab. Think of it as building a city-wide highway network: high-speed movement is available everywhere, but construction costs are steep.

CoWoS comes in several variants. CoWoS-S uses a solid silicon interposer and is what powers chips like the NVIDIA H100 and AMD MI300. It tops out at roughly 2,700mm² due to the reticle limit, the maximum area a lithography tool can expose in one shot. CoWoS-L extends beyond that constraint by placing small silicon chips (LSI chips) only at the high-speed interfaces and filling the rest with organic RDL. CoWoS-R goes further, replacing the silicon interposer entirely with an organic RDL layer, trading performance for cost.

Worth noting: CoWoS-L’s approach of placing silicon only where needed looks a lot like EMIB. AnandTech called it “TSMC’s answer to EMIB.” That TSMC built it at all is an implicit acknowledgment that full-area silicon interposers have limits.

EMIB: Intel’s Approach

Intel’s EMIB starts from the opposite premise. No interposer. Instead, small silicon bridges are embedded directly into the package substrate, appearing only where two chips need to talk at high speed. Everything else runs over standard organic substrate. If CoWoS is a city-wide highway network, EMIB is a bridge at a river crossing.

The practical difference shows up in utilization. Intel puts EMIB bridge wafer utilization at around 90%, versus roughly 60% for large interposers. Small pieces tile cleanly on a wafer with minimal waste, and since a significant chunk of CoWoS packaging cost comes from the silicon interposer, eliminating it changes the cost structure.

EMIB has been in production since 2017, starting with the Stratix 10 FPGA and running through server CPUs including Sapphire Rapids and Granite Rapids. Years of high-volume production history matter when an external customer is deciding whether to trust a packaging partner with their flagship chip.

What’s Actually Different

Cost: CoWoS carries higher packaging costs due to the large-area silicon interposer. EMIB is structurally cheaper because that interposer doesn’t exist. Actual cost differences vary by design and configuration, so blanket comparisons are imprecise.

Interconnect density: CoWoS allows traces across the entire interposer area, giving it an advantage in inter-chip bandwidth density. For GPUs requiring extreme throughput, CoWoS remains the better option.

Package scalability: EMIB scales by adding bridges wherever they’re needed. Intel’s EMIB-T specification supports a 120mm x 180mm package with 38 or more bridges. CoWoS-S is constrained by the reticle limit on interposer size, and while CoWoS-L extends that, it hasn’t matched EMIB’s scalability.

Design flexibility: EMIB allows mixing chips from entirely different process nodes in one package. A compute die on 3nm and an I/O die on 12nm can coexist. Each bridge connection can be individually optimized. For custom ASIC design, this flexibility has real value.

CoWoS and EMIB are not substitutes for each other. They address different use cases. For flagship GPU training chips demanding peak interconnect density, CoWoS wins. For custom ASICs where cost efficiency and design flexibility matter more, EMIB is the better fit. What’s interesting is that CoWoS is evolving toward EMIB’s core idea (local silicon bridges rather than full-area interposers). The principle of “connect only where you need it” is being absorbed by the broader industry.

3. How EMIB Is Evolving

EMIB is not static. As AI chip requirements change rapidly, the technology has branched in several directions.

Better Power Stability: EMIB-M

AI chips consume enormous power, and the problem isn’t consumption per se but the instability that comes with it. Noise on the power delivery network directly affects chip performance and reliability.

EMIB-M addresses this by embedding MIM capacitors (Metal-Insulator-Metal Capacitors) inside the bridge itself. Capacitors store charge temporarily and release it on demand. Integrating them into the interconnect acts as a power buffer, stabilizing supply to the chips. Think of it as embedding a voltage regulator directly into the connection layer.

Vertical Power Delivery: EMIB-T

The more significant evolution is EMIB-T, where “T” stands for TSV (Through-Silicon Via).

In conventional EMIB, signals and power travel laterally along the bridge surface, taking a detour to reach their destination. It’s like going from a building’s basement to its roof by walking up an external staircase. EMIB-T drills vertical through-holes (TSVs) through the bridge itself, allowing signals to travel straight through. The elevator shaft, rather than the fire escape.

Two things improve substantially. First, the power delivery path shortens and resistance drops. In the original EMIB “cantilever” geometry, power had to travel around the bridge to reach the chip. In EMIB-T, power comes from below through TSVs directly. For high-wattage AI chips, this is a meaningful difference. Second, integration with next-generation HBM4 and HBM4e becomes more natural. HBM itself stacks multiple DRAM layers using TSVs, so having TSVs in the connecting bridge simplifies the interface geometry.

EMIB-T’s specs are notable. Packages up to 120mm x 180mm with 38+ bridges and 12+ large dies. Bump pitch has tightened from 55μm in the first generation to 45μm and now 35μm, with 25μm in development. It also supports glass substrates in addition to organic ones, which matters because glass offers better thermal stability and enables finer routing, making it one of the key materials directions for next-generation packaging.

Combining Vertical and Horizontal: 3.5D

This is where Intel’s Foveros technology enters the picture.

If EMIB connects chips horizontally (the 2.5D model), Foveros stacks chips vertically (3D). Die on top of die, connected by TSVs and microbumps. The latest version, Foveros Direct, enables copper-to-copper direct bonding without bumps at all, which is what the industry calls hybrid bonding. Foveros is an Intel-developed technology that entered production in 2019 with the Lakefield processor and was later used in Meteor Lake.

Combine the two and you get 3.5D: chiplet stacks assembled via Foveros, then interconnected horizontally via EMIB. Apartment towers linked by bridges. This configuration allows vertical density increases while preserving horizontal scalability. Intel’s latest server CPU, Clearwater Forest, uses this 3.5D architecture: 18A process logic chiplets stacked on a base die via Foveros, with EMIB connecting those modules horizontally.

A Naming Collision Worth Noting

Broadcom also calls its XDSiP platform “3.5D,” which creates confusion. The underlying technology is completely different. Broadcom’s 3.5D is built on TSMC’s stack: CoWoS-L (LSI bridge + RDL interposer) for horizontal connectivity, and TSMC’s SoIC (System on Integrated Chips) for vertical stacking. SoIC is TSMC’s wafer-level direct bonding technology for 3D integration, the equivalent of Foveros in the TSMC ecosystem.

To summarize:

• Intel’s 3.5D = EMIB (horizontal) + Foveros (vertical). Both are Intel technologies.

• Broadcom’s 3.5D = CoWoS-L (horizontal) + SoIC (vertical). Both are TSMC technologies.

Same label, entirely different technology stacks. Always check whose technology sits underneath when you see “3.5D.”

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4. EMIB and Optical Interconnects

The way chips communicate across data centers is changing. Traditional electrical signaling over copper traces is hitting walls on both bandwidth and energy efficiency. CPO (Co-Packaged Optics) is emerging as a response: optical engines placed directly inside a chip package, transmitting data via light instead of copper.

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“Terafab Project launches in 7 days.”

I work as a semiconductor engineer in Silicon Valley. My network is full of engineers from NVIDIA, Broadcom, AMD, Qualcomm, SK Hynix, and basically every major chip company you can name. When I brought up Terafab, the reaction was unanimous.

“Lol.”

Terafab. Bigger than a gigafactory, hence “tera.” Logic, memory, and packaging all under one roof. Hundreds of billions of chips per year. And apparently he wants to smoke cigars and eat cheeseburgers inside the fab while doing it.

Terafab is bullshit.

At least that’s what a regular semiconductor engineer like me thinks.

But then again, Elon has always been that guy.

The one who solves problems that the experts in those fields said were unsolvable.

Rockets. Electric cars. Satellite internet. Every single time.

And yet, part of me can’t stop wondering how Elon is going to pull this off anyway.

This article covers two things. First, why running a semiconductor fab is so brutally hard, from the perspective of someone who has worked on the foundry side. Why the cigar comment made the industry laugh. What 2nm actually means. Why yield is not a problem you can throw money at.

Second, what Terafab might actually look like in practice. The moves already happening at Samsung Taylor. The Intel rumors. The packaging line in Texas where equipment is already being moved in.

This is Terafab story, seen through the eyes of an ordinary engineer.

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What’s confirmed and what’s vision

First, let’s separate known facts from Elon’s vision. Mixing them together clouds the judgment.

The confirmed facts: Elon first publicly mentioned Terafab at the annual shareholder meeting in November 2025, saying something to the effect of “even the best-case projections from foundries fall short of what we need.” The idea got more concrete during the Q4 2025 earnings call on January 28, 2026. Elon said Tesla needs to build “a very large fab in the US that includes logic, memory, and packaging,” and warned that chip supply constraints would hit within three to four years.

Tesla’s current chip manufacturing lineup is also confirmed. AI4 is made by Samsung. AI5 runs at both TSMC and Samsung in “slightly different versions” because the two foundries have fundamentally different process characteristics, so the software is designed to run on both. Samples in 2026, mass production in 2027. AI6 goes on Samsung’s 2nm SF2 process, locked in through a $16.5B long-term deal signed in July 2025 at Samsung’s Taylor, Texas fab, running through 2033. AI6 targets roughly 2x the performance of AI5, with mass production around mid-2028.

And Elon has said directly that AI7 onward would need “a different fab” or “something more adventurous.” The general read in the industry is that this refers to Terafab.

From here it shifts into Elon’s vision and press-based speculation. The target process node is reportedly 2nm, with a projected cost around $25B, though Tesla has never published detailed cost figures. The ramp from 100,000 wafer starts per month to eventually 1 million is based on Elon’s own statements. One million wafers a month, by the way, is roughly 70% of TSMC’s entire current monthly output. From a single facility. The figure of 100 to 200 billion chips per year comes from Elon’s own estimates of combined demand across Tesla, xAI, and SpaceX.

The “vision” part is Elon doing what Elon does: setting maximum targets. You don’t have to take it at face value. But the direction itself, that Tesla needs to control its own chip supply, is logically sound based on the confirmed facts alone.

“We’ll smoke cigars in the cleanroom”: what this one line reveals

If you want to compress the semiconductor industry’s reaction to Terafab into a single moment, it’s the cleanroom comment.

In a January 2026 interview on the Moonshots podcast, Elon said: “I think the latest fabs are building cleanrooms wrong. I’ll make a bet. If Tesla builds a 2nm fab, we’ll be able to eat cheeseburgers and smoke cigars inside it.”

His logic: if you keep the wafers sealed inside nitrogen-purged containers throughout the entire process, you don’t need to maintain the surrounding environment at ISO Class 1 levels. Wafer isolation is the key, not building-wide cleanliness.

Why did this get laughed at?

Modern advanced fabs run at ISO Class 1 to 2. That means fewer than 10 particles larger than 0.1 micrometers per cubic meter. One human breath releases millions of particles. A cigar? Billions of particles, plus organic contaminants that degrade EUV mirror surfaces and corrupt process chemistry. The grease from a cheeseburger works the same way. This is not metaphor. It is physics.

The FOUP-based wafer isolation Elon is describing is already standard practice. Wafers travel in sealed FOUPs inside fabs. That’s not new. The problem is that wafers have to leave the FOUP. When loading into lithography tools. When entering etching, deposition, CMP chambers. At those moments, the wafer is exposed to the surrounding environment. That exposure window is what determines yield.

TSMC spends billions on cleanrooms for a reason. It’s not ignorance or tradition. It’s because they’ve spent decades correlating environmental contamination data against defect density at the atomic level. At 2nm, a single transistor is tens of atoms across. One contamination event kills the whole chip.

Jensen Huang publicly warned Elon not to underestimate the difficulty. “Advanced semiconductor manufacturing is extremely hard. It’s not just building a factory. The engineering, the science, and the artistry of what TSMC does are extremely difficult.” To reporters, he went further, saying catching up to TSMC is “virtually impossible.”

The cleanroom comment matters not just because it’s technically wrong. It suggests Elon either doesn’t fully understand the complexity of semiconductor manufacturing yet, or is deliberately oversimplifying to sell the vision. Both are problems. The first means he’ll hit reality hard during execution. The second means he’s setting unrealistic expectations for investors.

Why Terafab doesn’t make sense, from someone who’s been inside a foundry

The cleanroom is just the beginning.

I’ve done post-silicon debug and yield improvement work at Samsung Foundry, Qualcomm, and AMD. I’ve seen how chips get made from both inside and outside the foundry. From that vantage point, Terafab has more than one or two realistic barriers.

1. The physical reality of building a fab

Building an advanced fab is not constructing a building. Exyte, a firm that has built roughly 300 fabs over 30 years, says a large advanced fab requires 30 to 40 million man-hours. 83,000 tons of steel. 9,000 kilometers of cable (longer than the distance from Seoul to Los Angeles). 600,000 cubic meters of concrete. Inside the building, you’re looking at about 40,000 square meters of cleanroom, 2,000 process tools, each one averaging 50 individual utility and process connections. That’s more than 100,000 pipe, gas, electrical, and coolant connections that all have to work together inside one facility.

In Taiwan, building a fab at this scale takes about 19 months. In the US? 38 months. Twice as long. Roughly twice the cost. And that’s using a company that has built fabs for decades. The US is slower because the permitting process is complex, environmental regulations are strict, 24-hour construction is hard to sustain given labor rules, and the pool of workers with fab construction experience is thin. Exyte’s CTO Herbert Blaschitz said Taiwan’s construction workforce is so experienced with fab builds that they can work without detailed drawings. That depth doesn’t exist in the US.

TSMC Arizona Fab 21 is the real-world data point. Announced in 2020, broke ground in 2021, original 2024 production target slipped due to workforce and supply chain problems. Samsung Taylor had its own delays from lack of customers and equipment delivery issues. These are the outcomes from companies that have been building fabs for decades. Tesla has never built one.

2. The technical complexity of 2nm

“2nm” is not just drawing smaller circuits. The transistor architecture itself changes.

FinFET, the 3D transistor structure the industry has used for years, hits its limits at 3nm. At 2nm you have to switch to Gate-All-Around, specifically nanosheet structures. FinFET wraps the gate around three sides of the channel. GAA wraps all four. This is the biggest architectural shift since the transition from planar to FinFET. You can reuse a lot of process modules, but nanosheet stacking uniformity control, new materials like ruthenium interconnects and high-k gate dielectrics, and techniques like subtractive metallization all have to be figured out from scratch.

The numbers: IBS estimates a 2nm fab at 50,000 wafer starts per month costs about $28B to build. That’s roughly 40% more than a 3nm fab at $20B. A 2nm wafer costs around $30,000 each to manufacture, about 50% more than 3nm. A large portion of that increase comes from the additional EUV lithography layers. Tape-out costs at 2nm run about $100M. One bad design decision, $100M gone.

3. Yield: the most brutal part

This is the real issue.

At 2nm, you’re fitting more than 300 million transistors into one square millimeter. A wafer goes through hundreds of process steps. If defect density drifts out of spec at any single step, yield collapses. Controlling this requires metrology, inspection, and process control working as one integrated system.

Intel 18A is the relevant case study. Volume production started in October 2025. Intel’s own CFO admitted that reaching “profitable yield levels” won’t happen until late 2026. A company with over 50 years of experience takes more than a year to get yield under control on a new node. Samsung Foundry’s 3nm GAA process is a more painful example. They were first to market with GAA in volume production, but the yield gap versus TSMC has made it extremely hard to win large customers. Being first did not mean being good.

Tesla starting at 2nm and nailing yield from the beginning? Having worked in yield improvement, I’d say that’s close to impossible.

4. Equipment: the bottleneck money can’t fix

EUV lithography scanners are made by one company on earth: ASML. The next-generation High-NA EUV at 0.55NA runs $350 to $400 million per unit. Intel has already locked up the first ten units of High-NA EUV production for its 14A node. If Tesla placed an order today, the tools wouldn’t arrive until 2028 at the earliest. Beyond EUV, a fab needs hundreds of other tool types across deposition, etching, CMP, and metrology, each with lead times ranging from six months to two years.

The workforce problem mirrors the equipment problem. SEMI projects that more than 60,000 semiconductor jobs in the US alone will go unfilled through 2030. With Intel, TSMC, and Samsung all building US fabs at the same time, adding Tesla to that competition would make the talent shortage significantly worse.

5. No design ecosystem: there’s no PDK

Building a fab is not enough to make chips. You need a PDK, a Process Design Kit. That means transistor models, design rules, standard cell libraries, I/O libraries, memory compilers, all of it. TSMC, Samsung, and Intel have developed their PDKs over decades. Developing a PDK for a new node and getting it certified with EDA tools takes one to two years on its own. If Tesla runs its own fab, it has to build the PDK from zero.

Does Tesla have the people to do that? Jim Keller left in 2018. Peter Bannon exited in 2025 when Dojo was wound down. Ganesh Venkataramanan left in 2023 to found DensityAI. There are meaningful gaps in Tesla’s custom silicon leadership right now.

6. Logic and memory together? The complexity of vertical integration

Logic and memory processes are fundamentally different. Different materials, different equipment, different contamination control standards. Logic fabs use copper for metal interconnects. DRAM relies on tungsten and molybdenum. Cross-contamination between those materials in a shared cleanroom destroys yield. Samsung does both logic and memory, but in separate fabs, run by separate organizations, on separate processes. Combining them under one roof is a completely different problem.

Why you can’t dismiss Elon outright

That’s the ordinary engineer’s read on Terafab.

But as I said at the start, Elon has heard this kind of skepticism his entire career. The important thing is that the industry’s “that won’t work” verdict has been wrong repeatedly.

SpaceX. In 2002, a guy with no aerospace background said he was going to build rockets. The first three Falcon 1 launches failed. When the company had enough money left for exactly one more attempt, the fourth launch succeeded. Elon himself said he gave it a 10% chance of success. Today SpaceX is the world’s largest commercial launch provider, launching rockets every few days.

Tesla nearly went bankrupt in 2008. Model 3 production became “production hell.” Bankruptcy rumors circulated every quarter. He pushed through anyway.

Gigafactory. Starlink. Both were dominated by skepticism at the start. And in every case, what got him through was a specific problem-solving framework he applies obsessively.

Elon’s five-step algorithm, applied to Terafab

Elon uses what Walter Isaacson called “The Algorithm” in his biography, a five-step problem-solving framework he applies across SpaceX and Tesla manufacturing. Here’s how it maps onto Terafab.

Step 1: Question every requirement. “Why does the entire cleanroom need to be ISO Class 1?” The cigar comment is technically oversimplified, but asking “why?” about something TSMC has taken for granted for 37 years is exactly this step.

Step 2: Delete. “The best part is no part.” Semiconductor process steps are so interdependent that there’s far less room to delete than in rocket manufacturing. But in the fab construction process itself, there’s likely plenty of inefficiency that can be stripped out.

Step 3: Simplify and optimize. “The most common mistake of smart engineers is optimizing something that shouldn’t exist.” Tesla famously spent huge effort automating a battery mat step in Model 3 production before realizing the mat itself was unnecessary.

Step 4: Accelerate. “If you’re digging your own grave, don’t dig faster.” Speed only comes after steps one through three. Cutting the US fab construction cycle from 38 months is where this applies.

Step 5: Automate. “The big mistake in my factories was trying to automate every step from the beginning.” The lesson from Model 3 production hell. Terafab won’t be a fully automated 2nm facility from day one. The realistic path is small scale, learn, then expand.

Can these five steps be applied to the semiconductor process itself? Honestly, I’m still pretty skeptical. But I think they can be applied to fab construction and fab operations. Not the process chemistry, but the infrastructure, logistics, and construction methodology around it. There are almost certainly inefficiencies that the fab industry treats as standard practice, and that’s probably where Elon starts.

What it actually looks like in practice

The most important question isn’t “will Terafab happen or not.” It’s “if it happens, what form does it take.”

Samsung Taylor: the zeroth step

The real significance of the $16.5B deal is not the contract size. It’s that Elon reportedly wants to go inside Samsung’s production lines and work directly on improving efficiency. That kind of access is not available to a typical fabless customer. It was only possible because Samsung’s Taylor fab was sitting largely empty without committed customers.

There’s also news from today, March 17th. Samsung is preparing to build a second fab dedicated to AI6 at the Taylor campus. The first $25B fab hasn’t even ramped yet, and they’re already starting a second one. That signals Tesla’s chip demand will outstrip a single fab’s capacity. The Taylor campus can reportedly accommodate up to ten fabs.

My read: the experience Tesla accumulates at Samsung Taylor, the process engineering knowledge, the yield improvement methodology, the equipment operating expertise, that’s the zeroth step of Terafab.

Packaging: the most certain first move

According to DigiTimes, SpaceX’s FOPLP (Fan-Out Panel-Level Packaging) line in Texas started receiving equipment in September 2025. Target is low-volume production in Q3 2026, with full production in Q1 2027. It starts with RF chip packaging for Starlink satellites, but that same infrastructure can be directly extended to Tesla AI chip packaging.

Why does packaging matter. The biggest physical bottleneck in the AI chip market right now is TSMC’s CoWoS packaging capacity. NVIDIA, AMD, and Broadcom are all fighting over CoWoS allocation. If Tesla controls its own packaging line, it escapes that bottleneck entirely. Packaging also has a much lower barrier to entry than wafer fabrication. No EUV required. Cleanroom standards are less demanding. This is the most realistic path to meaningful results within two to three years.

Intel: the door is open

Sticking to confirmed facts: Elon has publicly said he thinks there’s something to do with Intel. Intel Foundry desperately needs external customers (operating loss of $2.26B in Q4 2024). DigiTimes has reported that Dojo 3 chip packaging may be handled at Intel’s Arizona facility. If that’s accurate, a working relationship already exists.

From here it’s speculation. A full Tesla acquisition of Intel is not realistic. But a long-term lease of specific Intel Foundry fab lines, a JV-style co-investment, or a large advanced packaging customer relationship is all plausible. Intel CEO Lip-Bu Tan has admitted directly that “14A cannot move forward without external customers.” Tesla is one of the very few companies with the volume to make that argument credible.

The Battery Day lesson: the real goal is leverage

At Battery Day in 2020, Elon announced in-house production of 4680 cells. The target of 100 GWh by 2022 was badly missed. But eventually it worked, and in the process Tesla built negotiating leverage over Panasonic and CATL. It was not full independence, but the existence of the option, “we can make these ourselves,” changed the negotiating dynamic completely.

Terafab is likely the same pattern. The end goal is not “100% self-manufactured chips.” It’s “we will not be held hostage by chip supply.” The announcement of building a fab is itself a negotiating card against TSMC and Samsung. That works even before the fab ever turns on.

Between bullshit and vision

I’m a working semiconductor engineer. I’ve been through Samsung, Qualcomm, and AMD. I’ve seen chips designed, manufactured, tested, and ramped into production. I have enough experience in this field to speak with some credibility about how hard semiconductor manufacturing actually is.

So when I look at Terafab as stated, I think there’s a large gap between the vision and reality. The cigar comment, taken at face value, sounds like someone who hasn’t fully internalized what semiconductor manufacturing involves.

At the same time, I think Tesla’s semiconductor insourcing will move forward in some form. There is clear internal demand at serious scale (FSD, Cybercab, Optimus, xAI). Manufacturing partner diversification is already underway. The foundry learning that’s starting at Samsung Taylor is real. The FOPLP line in Texas is physically in motion. And above all, there’s Elon’s consistent track record and The Algorithm.

It makes sense that Terafab looks like bullshit to a lot of people.

SpaceX did too. So did Tesla. So did Starlink.

Just a few years ago, the semiconductor industry’s biggest talking point was “which company will capture the leading-edge nanometer process first.” Every semiconductor company rushed to emphasize how many nanometers their products were. However, in 2026, intertwined with the AI era, the semiconductor industry’s paradigm is passing through a clear turning point.

The Limits of Process Scaling

Samsung and TSMC are approaching 2nm process mass production, and Intel has entered preparation for 18A (1.8nm-class) process manufacturing. But as processes become finer, semiconductors hit three fundamental limits.

First, cost increases overwhelm performance gains. From 7nm to 5nm, from 5nm to 3nm, wafer costs increase 30-40% per node while performance improves only 10-15%. Development costs and mask expenses for each process step increase exponentially, rapidly deteriorating economics.

Second, physical limits have become visible. As transistor gate lengths shrink to several nanometers, physical limits like quantum tunneling, leakage current, and process variation have materialized. Overcoming these requires new transistor structures like GAA (Gate-All-Around), which also drive costs skyward.

Third, AI workloads can’t be solved by process alone. AI chip bottlenecks aren’t computational speed but data movement. No matter how fast you make GPU cores, performance stagnates if memory bandwidth is insufficient. Process scaling can’t solve this problem.

Three Critical Advantages of Packaging

Packaging provides a practical solution to elevate system performance while circumventing process scaling limits.

First, heterogeneous integration is possible. Chips made with different processes can be combined in one package. AMD’s Instinct MI400 series unveiled at CES 2026 is representative. The MI455X integrates 12 compute dies and I/O dies made with TSMC 2nm and 3nm processes in one package. Producing each die at its optimal process node and integrating at the packaging stage maximizes cost efficiency—far more economical than implementing all functions on a single cutting-edge process.

Second, it fundamentally solves memory bandwidth problems. NVIDIA H200 provides HBM3E 141GB and 4.8TB/s memory bandwidth. AMD MI455X achieves 432GB memory capacity and 19.6TB/s bandwidth with 12 HBM4 stacks. This is possible because GPU dies and HBM are placed millimeters apart on a 2.5D interposer. The same performance would be physically impossible with GDDR memory on a PCB substrate. Shorter signal distances increase bandwidth and reduce power consumption.

Third, it secures both yield and flexibility. Large monolithic dies see yields drop exponentially as area increases. If a wafer has several defects, larger dies are more likely to encounter them. Dividing into multiple small dies keeps individual die yields high, and only defective dies need replacement. Intel’s Core Ultra Series 3 (Panther Lake) announced at CES 2026 separately manufactures CPU, GPU, and I/O tiles and stacks them with Foveros 3D packaging. If one tile has issues, only that tile needs replacement rather than discarding the entire unit.

The definition of a “good chip” has changed. High transistor density alone isn’t enough—actual performance is determined by how efficiently multiple dies are connected, power is supplied, and heat is removed. All of this falls under packaging technology.

In conclusion, as of 2026, semiconductor industry winners are determined not by “who has the finest process” but by “who has secured advanced packaging capacity.”

2. The Three Evolution Axes of Semiconductor Packaging

Packaging technologies can be divided into three axes.

Area expansion axis: Meeting demand for larger chips by creating bigger packages. Starting from 2.5D interposers (CoWoS, EMIB), evolving beyond wafer size limits to panel-level packaging (CoPoS).

Density maximization axis: Stacking chips vertically to increase connection density. Hybrid bonding (SoIC, Foveros Direct, X-Cube) is core, with HBM stacks also belonging here.

Bandwidth breakthrough axis: Increasing data transfer speeds between chips and packages. Represented by chiplet standards like UCIe and optical interconnects like CPO (Co-Packaged Optics).

These three axes aren’t independent. For example, chips can be stacked with hybrid bonding on a 2.5D interposer, communicate via UCIe, and send data outside the package via CPO. Actual AI systems are built combining these technologies.

2.1 Area Expansion Axis: 2.5D → Panel Level

AI chips keep getting larger. NVIDIA’s GB200 Superchip is a large package integrating two Blackwell GPUs and one Grace CPU. AMD’s MI455X also integrates 12 HBM4 dies and 12 compute/I/O dies made with 2nm/3nm processes in one package. The problem is that manufacturing such large packages on 12-inch (300mm) wafers is inefficient. Placing rectangular packages on round wafers wastes edge area, and wafer output per wafer drops sharply as packages grow.

CoWoS is currently the most widely used 2.5D interposer technology, but as large-area package demand continues growing, it hits wafer-based production limits. TSMC is developing CoPoS (Chip on Panel on Substrate) to address this. Using large square panels (310mm x 310mm) as substrates instead of wafers significantly improves area utilization and enables larger packages.

Industry reports indicate CoPoS will go through pilot lines in 2026 targeting mass production in 2028-2029. However, recent Nomura reports suggest CoPoS mass production might delay to 2029-2030. Transitioning to panel level requires changes across equipment, materials, and processes, taking time, but long-term it’s likely to become the mainstream production method for large AI packages. NVIDIA is expected to be the first major customer.

Samsung is also developing FOPLP (Fan-Out Panel Level Packaging), and Powertech has been mass-producing under the name PiFO since 2019. Fan-out originally makes redistribution layers wider than chips to increase I/O density—doing this at panel level simultaneously achieves large area and high density. However, most industry observers see TSMC CoPoS as more likely to capture the market first.

2.2 Density Maximization Axis: Hybrid Bonding & 3D Stacking

2.5D places chips side by side horizontally. 3D stacks them vertically. Vertical stacking can integrate more functions in the same area and drastically reduces chip-to-chip distance, simultaneously improving bandwidth and power efficiency.

Traditional 3D packaging used micro bumps—solder balls placed at tens of micrometers pitch to connect stacked chips. But entering the AI era, micro bump limitations became clear. Pitch is hard to reduce further, and low connection density limits bandwidth.

Hybrid bonding is a game changer. It simultaneously bonds copper (Cu) pads and silicon oxide (SiO₂), creating direct Cu-Cu connections without solder. Pitch can be reduced below 10 micrometers, and TSMC is already mass-producing with SoIC technology. Intel’s Foveros Direct has 9-micrometer pitch for gen-1, targeting 3-micrometer for gen-2. Samsung’s X-Cube is also hybrid bonding-based, with 2026 mass production timeline discussed.

As pitch shrinks, connection point counts increase exponentially. If you can make 10x more connections in the same area, data transfer bandwidth also increases 10x while power per signal line decreases. This is hybrid bonding’s core value.

However, hybrid bonding has very high technical difficulty. Cu surfaces must be nanometer-level flat, and even a single dust particle causes bonding failure. Stacking materials with different thermal expansion coefficients creates stress during temperature changes that can cause cracks. Achieving high yields requires extremely precise control of surface treatment, alignment, bonding pressure, and heat treatment conditions.

HBM is also a representative 3D stacking case. Current HBM3E mainstream is 8-12 stack layers, with HBM4 planned up to 16 layers. However, entire HBM stacks won’t immediately transition to hybrid bonding. A hybrid approach is realistic: DRAM-to-DRAM connections continue using micro bumps and TSVs, with hybrid bonding applied only between logic dies and the first DRAM layer. Converting everything to hybrid bonding first requires solving yield and cost issues.

2.3 Bandwidth Breakthrough Axis: UCIe Chiplets + CPO Optical I/O

As chiplet architecture spreads, scenarios combining chips from different companies are becoming reality. For example, to put Company A’s CPU chiplet, Company B’s AI accelerator chiplet, and Company C’s I/O chiplet in one package, all three chips must follow common interface specifications. That’s UCIe (Universal Chiplet Interconnect Express).

UCIe is a standard with participation from major industry players including Intel, AMD, TSMC, Samsung, ARM, and Google. UCIe 1.0 came out in 2022, with UCIe 2.0 in 2024 and UCIe 3.0 in 2025, continuously upgrading bandwidth and scalability. UCIe includes physical layer (PHY), die-to-die link protocols, and packaging guidelines.

UCIe’s core value is ecosystem expansion. Previously AMD only connected its own chiplets and Intel only its own tiles, but as UCIe matures, customers can directly combine “Intel CPU + AMD GPU + Marvell I/O.” This has potential to change the semiconductor industry structure itself. Of course, actualizing this requires solving ecosystem issues like IP licensing, testing, and security, but the technical foundation is already laid.

Meanwhile, I/O leaving packages is also a bottleneck. AI accelerators communicate with other accelerators through network switches, and switch bandwidth requirements are exploding. Traditional electrical signal-based SerDes faces serious power consumption and signal integrity issues beyond 50Gbps, 100Gbps.

CPO (Co-Packaged Optics) solves this with optical communication. Optical transceivers are attached inside or right next to packages, minimizing the distance for electrical-to-optical conversion. Previously optical modules plugged into QSFP cages tens of centimeters from switch ASICs—CPO reduces this distance to millimeters. Power efficiency greatly improves and higher bandwidth can be achieved.

CPO’s technical challenge is integrating optical engines with electronic chips. Silicon photonics technology can integrate optical waveguides and modulators on wafers, but yield and alignment accuracy are key. Also, where to place laser light sources and how to cool them remain homework. Nevertheless, because electrical I/O physical limits are clear, CPO seems an unavoidable direction.

“Sand from Centuries Past: Send Future Voices Fast”
This was the title presented by Professor Charles K. Kao, the ‘Father of Fiber Optics,’ during his Nobel Prize...

3. 2030 Outlook: Three Decisive Factors

Large-Scale and 3D Simultaneously

Semiconductor packaging will evolve in two directions: “larger” and “denser.”

Area expansion: AI chips continue growing. NVIDIA’s Rubin architecture is expected to require larger packages than existing Blackwell. Wafer-based CoWoS expansion continues, but ultra-large package demand partially shifts to panel level like CoPoS. If 2029 CoPoS mass production succeeds, panel level will become mainstream for large AI packages in the early 2030s. However, as Nomura reports noted, mass production timing might delay to 2029-2030.

Density maximization: 3D stacks spread to pack more functions in the same area. Hybrid bonding pitch drops below 3 micrometers based on Intel Foveros Direct gen-2. HBM can go beyond 16 layers to 20, 24 layers. Both SK hynix and Samsung are researching 16+ layer HBM stacks.

Hybrid structures placing multiple 3D stacks on large-area packages are natural. Area and density axes ultimately merge. TSMC already offers combinations placing SoIC on CoWoS. NVIDIA Rubin is also expected to combine CoWoS-L and SoIC. The same approach works at panel level.

Power Delivery and Substrate Innovation Determine Performance

Backside Power Delivery: Intel PowerVia was already applied in Arrow Lake and continues expanding in next-gen products. TSMC is known to introduce BSPDN (BackSide Power Delivery Network) in the A16 process (1.6nm-class). Moving power lines to the wafer backside leaves the frontside for signal lines only, increasing routing headroom and reducing IR drop (voltage drop).

As backside power becomes mainstream in 2026-2027, package power network design also changes. With power wiring on the backside, the backside can also be used for cooling. Extracting heat from both front and back sides can lower temperatures even in high-power-density chips. Combined with direct-to-chip liquid cooling, this becomes core technology for stably operating 1,200W+ AI packages.

Glass Substrate: Traditional organic substrates made from polymer materials like epoxy resin have large thermal expansion coefficients and limited flatness. Glass substrates excel in flatness with thermal expansion coefficients close to silicon. They provide 10x higher interconnect density and superior structural stability versus organic substrates.

Intel officially announced glass substrates for 2027-2029 market introduction and operates dedicated glass substrate facilities in Arizona. TSMC is also validating glass substrates in cooperation with Corning. Glass substrates solve warpage and wiring precision problems in ultra-large packages. Even hundreds-of-square-centimeter packages difficult with organic substrates become possible with glass.

RDL (Re-Distribution Layer) advancement: Redistribution layers core to CoWoS-R and fan-out packaging also evolve. Wiring pitch drops below 2 micrometers and multi-layering advances, simultaneously improving signal integrity and power efficiency. TSMC plans major RDL technology enhancements in CoWoS with 9.5x reticle size scheduled for 2027 mass production.

Packaging Becomes a Comprehensive Battle of Technology, Capacity, and Ecosystem

2030 semiconductor industry winners will have all three.

Technology: Not just cutting-edge processes but advanced packaging technologies. Must offer all options including 2.5D (CoWoS, EMIB), 3D (SoIC, Foveros, X-Cube), hybrid bonding, panel level (CoPoS), CPO, backside power, glass substrates to attract customers. This is why TSMC aims to provide CoWoS, SoIC, and CoPoS.

Capacity: Technology alone is useless without production capacity. TSMC dominates now because it secured CoWoS capacity faster than others. TSMC plans to reach 90,000-100,000 wafers monthly CoWoS capacity by end of 2026. Samsung and Intel are investing trillions in capacity expansion but haven’t caught TSMC yet.

Ecosystem: Not just making chips, but platforms unifying materials, equipment, OSATs, IP companies, and customers. TSMC’s OIP (Open Innovation Platform) and Intel Foundry Services both aim to secure ecosystems. Standards like UCIe are also ecosystem expansion tools. NVIDIA securing 50%+ of TSMC CoWoS capacity doesn’t just mean good technology—it means preempting TSMC’s entire ecosystem.

Technology alone, capacity alone, or customers alone aren’t enough. Platforms that can supply process, packaging, substrates, equipment, inspection, cooling, and optics as one bundle win.

4. Promising Semiconductor Packaging Companies: Where Value Is Created

Foundry War: Vertical Integration of Foundry and Packaging Technology

TSMC currently dominates advanced packaging markets. Based on overwhelming CoWoS share, NVIDIA alone secured 50%+ capacity. SoIC is already mass-producing, with CoPoS targeting 2029 mass production. TSMC’s strength isn’t just technology but capacity and ecosystem. TSMC is building advanced packaging facilities not just in Taiwan but in Kumamoto, Japan and Arizona, USA. End-2026 CoWoS monthly capacity is projected to reach 90,000-100,000 wafers.

Samsung Electronics has I-Cube 2.5D and X-Cube 3D packaging but lags TSMC in capacity and ecosystem. Samsung’s strength is vertical integration of both HBM and foundry. It can differentiate in logic+HBM integrated packaging, but short-term catch-up is difficult since TSMC already preempted the CoWoS market. Samsung targets 2026 X-Cube mass production.

Intel has the broadest technology portfolio with EMIB + Foveros + PowerVia + glass substrates. Backside power (PowerVia) was already applied in Arrow Lake, with glass substrates under development in dedicated Arizona facilities. Through Intel Foundry Services it aims to provide packaging to external customers, but customer acquisition is key. Intel challenges TSMC with a “process + packaging bundle” strategy combining 18A (1.8nm-class) process and advanced packaging.

OSAT Rise: From Simple Assembly to Core Partner

The AI era changed OSAT positions. Previously “foundries make chips, OSATs just assemble” was the perception, but in advanced packaging OSATs became core.

ASE Technology Holding is the world’s largest OSAT. Advanced packaging revenue increased 30%+ year-over-year from 2024-2025. ASE provides fan-out, 2.5D, and 3D stacking. Major customers include NVIDIA, AMD, Qualcomm, expanding dedicated advanced packaging lines in Taiwan and China. Over 40% of 2025 capex went to advanced packaging.

Amkor Technology broke ground on an Arizona advanced packaging campus with total investment exceeding $2 billion. Slated for 2027 operation, it received $400 million+ in CHIPS Act funding in 2024. NVIDIA collaboration was disclosed, with particular strength in HBM packaging. Also closely cooperating with SK hynix.

JCET Group is China’s largest OSAT. Despite US-China tech competition, it’s accelerating AI and advanced packaging investment. Expanded fan-out and 2.5D packaging lines in 2024-2025. As China’s domestic AI chip demand grows, JCET’s growth potential can’t be ignored.

HBM Manufacturers Enter Packaging

No AI chips without HBM, no finished products without packaging connecting HBM to logic. So HBM manufacturers are strengthening packaging capabilities.

SK hynix is #1 in HBM market share. Estimated 50%+ HBM market share as of 2024. Started HBM3E 12-layer mass production in 2024, unveiled 16-layer HBM4 samples in November 2025. Targeting H1 2027 mass production. Established advanced packaging R&D center in Indiana, USA, expanding cooperation with Amkor. If SK hynix further builds packaging capabilities, it could make logic+HBM finished products directly without TSMC dependency.

Samsung Electronics started HBM3E mass production in H2 2024, rapidly increasing supply in 2025. Samsung is the only company with memory, foundry, and packaging. Samsung Electro-Mechanics is #1 in FC-BGA substrate market share, supplying substrates for products like NVIDIA H100, H200, Blackwell GB200. FC-BGA revenue grew 30%+ year-over-year in 2024. Samsung’s challenge is bringing foundry and packaging capacity to TSMC levels.

Micron Technology is #3 in HBM market. In 2025 Singapore investment announcement, Micron mentioned its HBM advanced packaging plant could contribute to supply from 2027. Plans to invest ~$7 billion in Singapore advanced packaging facilities.

CPO and Networking Silicon

Broadcom most aggressively pursues CPO. The Tomahawk 6 switch announced in December 2025 applies 3rd-gen CPO technology based on 200Gbps per lane. Improves power efficiency 40%+ versus electrical SerDes while providing total 25.6Tbps bandwidth. Slated for 2026-2027 mass production, already cooperating with hyperscalers like Google, Meta, AWS, Microsoft. Broadcom’s CPO will first apply to networking switches short-term but is expected to expand to GPUs and AI accelerators mid-to-long term.

Marvell Technology is also investing in datacenter networking and silicon photonics. Marvell is developing solutions combining PAM4 DSP (Digital Signal Processing) and optical interconnect technology.

POET Technologies attacks the CPO market with a unique platform called Optical Interposer. Traditional interposers connect electronic chips with metal wiring—POET integrates optical devices like waveguides, lasers, and filters inside the interposer. Fully CMOS-compatible and wafer-scale manufacturable, significantly reducing cost versus traditional optical modules.

Ayar Labs and Lightmatter startups are also developing intra-chip optical interconnect technology. They aim to pull the electrical-to-optical conversion point deeper inside chips, targeting optical conversion even for die-to-die connections inside GPUs.

The CPO market’s turning point is 2026-2027—when companies transitioning from pilot to mass production are decided and hyperscalers begin large-scale adoption.

Conclusion

Post-2026 AI semiconductor competition has shifted focus from “who makes better dies” to “who can assemble and ship systems faster, larger, and more reliably.”

Process scaling remains important, but that performance can’t become systems without packaging. This is why NVIDIA CEO Jensen Huang said in 2024 earnings calls “advanced packaging capacity quadrupled over two years yet remains a bottleneck.” Even making HBM and fabricating logic dies in cutting-edge processes, products can’t ship without 2.5D assembly slots.

The next 3-5 years will be the packaging war era. Winners are determined by who makes larger packages (CoPoS), stacks denser (hybrid bonding), connects faster (UCIe, CPO), and cools more efficiently (microfluidic, backside power).

Winners will be platforms with technology, capacity, and ecosystems. TSMC currently leads, but Intel’s glass substrates and backside power, Samsung’s HBM+foundry vertical integration could be wildcards. Korean companies have strengths in HBM and substrates, but without controlling entire packaging platforms must cede much value-add to TSMC.

Ultimately, the 2030 semiconductor industry landscape will be determined by “who controls packaging ecosystems.”

In Q4 2025, Intel Foundry posted revenue of $4.5 billion alongside an operating loss of $2.5 billion. CEO Lip-Bu Tan admitted that “the company invested too much, too fast, without sufficient demand,” and Intel’s SEC filing included risk language to the effect that the company has yet to secure meaningful external foundry customers at scale on any of its nodes.

Framing Intel Foundry’s difficulties as simply a matter of “trust deficit” misses the point. The foundry business is far more technical, far more structural, and far more dependent on the compounding effects of time and volume than that narrative suggests.

This article organizes that complex reality around three axes. First, why is the foundry business so difficult for latecomers to break into? Second, what are Intel’s genuine strengths and structural limitations on the 2nm battlefield? Third, what must Intel choose and what must it sacrifice in order to survive?

Disclaimer: This article is a personal analysis based on the author’s foundry industry experience, publicly available information, and observable industry trends. Some content includes estimates and interpretation. Facts are subject to change, and this article does not constitute investment advice, a recommendation to buy or sell securities, or legal or accounting advice. The author accepts no responsibility for any decisions made based on this content. All final judgments and verification are the sole responsibility of the reader.

1. Why Is the Foundry Business So Hard? The Moat Built from Technical Accumulation

The core barrier to entry in the foundry business is not any single technology. It is the compounding effect of technical assets built up over decades. Tracing the full journey from chip design to volume production reveals a wall at every stage that latecomers struggle to climb. This section examines the key technologies that define the foundry industry.

The Design Entry Requirement: PDK and IP Ecosystem

Before a fabless company can manufacture chips at a given foundry, it needs a PDK, or Process Design Kit. A PDK packages a foundry’s process information into a form that design engineers can actually use. It includes the layouts of basic devices like transistors, SPICE models for simulating electrical behavior, thousands of design rules, and technology files that allow EDA tools to analyze designs against the physical characteristics of that specific process.

The most important concept here is MHC, or Model-to-Hardware Correlation. In plain terms, MHC asks: “Does the silicon behave the way the simulation predicted?” How accurately a PDK’s SPICE models reflect the actual behavior of fabricated silicon is one of the most critical measures of a foundry’s technical competence. What happens when MHC breaks down? A customer who invested tens of millions of dollars to tape out a chip discovers it doesn’t perform as expected. That customer never comes back.

TSMC’s PDK is as powerful as it is because over thirty-plus years of producing chips for thousands of customers, the accumulated silicon data has continuously recalibrated and refined model accuracy. Where does Intel stand by comparison? Intel’s 18A PDK 1.0 was released in July 2024, and the company has reported more than 100 tapeouts, but by most industry assessments, it remains far from reaching the level of MHC validation that TSMC has achieved.

A PDK alone isn’t enough, either. In SoC design, complex functional blocks like CPU cores, PCIe interfaces, and DDR controllers are typically sourced as pre-verified IP. Those IP blocks must be silicon-proven on the specific process at the specific foundry. IP validated for TSMC cannot simply be ported to Intel 18A. Physical design must be redone, timing constraints must be re-established, and silicon validation must start from scratch. That process takes a minimum of 12 to 18 months.

TSMC’s Open Innovation Platform has thousands of silicon-proven IP blocks registered to it. The reason IP vendors build for TSMC first is simple: TSMC has the most customers, so the ROI is highest. Because Intel has fewer customers, it has less IP, and because it has less IP, fewer customers come. The cycle feeds on itself.

Manufacturing Capability: The Invisible Asset Called BKM

In semiconductor manufacturing, BKM stands for Best Known Methods. These are the best currently understood approaches to each of the hundreds to thousands of process steps in an advanced node. The optimal exposure conditions for lithography, the gas flow and pressure combinations for etching, the polish time and pressure for CMP — BKM is the optimized combination of every parameter. Critically, today’s BKM is not the final answer. When a better method is found, it gets updated.

BKM isn’t learned by reading papers in a lab. It comes from running actual wafers, accumulating process response data across a wide variety of design patterns, discovering unexpected defect modes, and finding solutions. The more wafers you run, the faster you find and resolve problems.

This is where the scale effect of foundries kicks in. TSMC simultaneously produces chips for hundreds of customers with vastly different designs, generating enormous wafer volumes. Through that process, solutions to diverse defect modes are codified as BKM, and every customer on the same process benefits. Intel Foundry, with almost no external customers, is accumulating BKM primarily through its own x86 processors. It lacks process data across the wide variety of design patterns found in mobile APs, AI accelerators, networking chips, and beyond.

Yield and Cost: The Core Equation of Foundry Economics

All of this technical accumulation converges on yield. The single most critical variable determining foundry economics is defect density, or D₀, which represents the number of critical defects per unit area of wafer.

At D₀ = 0.40 with a die area of 1 cm², yield is roughly 67%. Improve D₀ to 0.10 and yield jumps to around 90%. Translating that yield difference into dollars reveals the severity of the problem. The cost of a single leading-edge 2nm-class wafer is estimated at over $20,000. At 65% yield, 65 out of 100 dies per wafer are good. At 90%, 90 are. The per-die cost difference exceeds 38%.

Add fab utilization to the equation. A leading-edge fab costs billions of dollars per year to operate, and those fixed costs accrue whether or not wafers are running. At 50% utilization, fixed cost allocation per die nearly doubles compared to 80% utilization. Intel Foundry losing $2.5 billion per quarter is a structural consequence of low yield and low utilization compounding simultaneously.

Yield improvement follows a learning curve. Early on, systematic factors like equipment setup, process conditions, and process windows dominate defect behavior. Over time, the contest shifts to how quickly you can drive down random defect density. In that phase, the decisive variable is how many wafers, with how many diverse patterns, are run how frequently. More volume means defects are observed faster, root causes are isolated sooner, and BKM gets updated more rapidly. Yield matures faster within the same timeframe.

This is why large foundries can immediately ramp utilization at the start of a new node and simultaneously produce a diverse mix of customer designs, maximizing the speed of learning. A foundry with limited external volume has less learning data, slower yield maturation, and a structural disadvantage in per-wafer cost and delivery reliability. That cost and reliability gap makes it harder to win customers, perpetuating volume shortfall, which slows yield learning further. The cycle compounds.

PDK maturity, BKM depth, and yield learning speed are all functions of time and volume. Once the virtuous cycle starts spinning, the gap with latecomers widens exponentially. That is the substance of the moat TSMC has been building for more than thirty years.

2. Where Does Intel Foundry Stand Today?

Intel 18A: Production Has Started, But There Are Still No External Customers

Intel 18A is understood to have entered serious production ramp in the second half of 2025. Intel has positioned 18A as the process that first brings RibbonFET (GAA) and PowerVia (backside power delivery) to high-volume manufacturing simultaneously, and has emphasized that this combination represents the first instance of that approach reaching production scale. The Core Ultra Series 3 — the Panther Lake family — has been cited as the first product on the node, with Clearwater Forest, the server variant, also named on the roadmap. There have been reports of CEO Lip-Bu Tan offering positive assessments suggesting 18A progress has been ahead of expectations.

Yield has not been officially disclosed, and various estimates circulate in the press and industry. Some sources have floated numbers in the low-to-mid 60% range. On the PDK side, Intel announced the release of 18A PDK 1.0 in July 2024, and tapeouts are ongoing.

The fundamental issue, however, is who that technical progress is for. Everything known about 18A’s advancement is largely anchored to Intel’s own products. Intel’s SEC filings have repeatedly included risk language noting that external customer volume remains limited. In short: the process is running, but the external volume, trust, and scale that a foundry business actually requires have yet to be demonstrated.

The external-customer-facing variant, 18A-P, is in preparation. There are indications that the 18A-P PDK has been delivered to select customers for evaluation, and some observers expect customer qualification and production discussions to accelerate around 2026. Ultimately, the true test for Intel as a foundry is not the internal success of 18A itself, but whether external customers actually commit volume to 18A-P.

Compared to TSMC N2: Behind on Density, Cost, and Ecosystem

Intel 18A’s direct competitor is TSMC N2. The two processes compete in the same 2nm-class generation, but the axes on which each is perceived to be strong differ considerably.

Intel has made strong claims about performance and power efficiency. The company has presented data showing performance gains at equivalent voltage, or power savings at equivalent performance, under specific comparison conditions using ARM cores, pointing to PowerVia as the underlying technology. PowerVia separates the power network to the backside of the chip, freeing up frontside routing resources for signal and reducing IR drop. The logic is compelling on paper, promising to alleviate design bottlenecks. That said, process-to-process performance comparisons depend heavily on product configuration and design methodology, and for external customers, silicon reproducibility and production data will ultimately matter most.

On density, TSMC holds a clear lead. TSMC N2 achieves 313 million transistors per square millimeter versus Intel 18A’s 238 million. Higher density means smaller dies for the same chip, which means lower cost per die. PowerVia does reclaim some frontside area, so the “effective density” gap may be smaller than the raw numbers suggest, but the additional process steps required for backside power delivery likely push Intel’s wafer manufacturing cost higher.

Yield gaps are also expected to be meaningful. Exact figures aren’t available, but Intel has not publicly disclosed 18A yield numbers, while TSMC has a longstanding industry reputation for rapid yield ramp and volume-driven learning. More fundamentally, the real comparison isn’t the current yield percentage but the rate of maturation. As the yield economics discussed earlier make clear, a difference in ramp speed directly translates into differences in per-die cost and delivery reliability.

The ecosystem comparison is almost impossible to make on equal terms. TSMC’s OIP has thousands of silicon-proven IP entries. Intel 18A’s IP ecosystem is just beginning to be built. More fundamentally, Intel’s PowerVia is incompatible with existing front-side power delivery IP. Adapting to a backside power delivery process requires fundamentally redesigning the power routing architecture, which is not a simple port but something closer to a full IP redevelopment. TSMC, meanwhile, is running a dual-track strategy: FSPD on N2 and BSPD on A16 (targeting 2026 to 2027), giving customers a choice. Intel is single-track on BSPD.

Taken together, Intel’s positioning is clear. There is a competitive case in premium HPC and AI markets where performance matters most, but mobile and IoT markets driven by cost and density remain structurally out of reach for now. The addressable market is inherently narrow.

Samsung Foundry: A Cautionary Tale and a Reemerging Competitor

Intel is not the only contestant on the 2nm battlefield. Samsung, the other IDM running a foundry business, is rejoining the fight.

Samsung walked the road Intel is now trying to walk, and paid dearly for it. When the Qualcomm Snapdragon 8 Gen 1 was manufactured on Samsung’s 4nm process, it became notorious for heat and poor power efficiency, and Qualcomm’s flagship volume shifted to TSMC. Samsung’s 3nm GAA was announced as a technical breakthrough, but the market judged it by production reliability and supply stability, not announcements. Samsung lost customer confidence at the leading edge, and the identity of its foundry business was shaken.

From the second half of 2025, however, the atmosphere has been shifting. Samsung has put its SF2 (2nm) roadmap back at the center of its narrative and has been signaling “this time is different” through actual tapeouts and productization plans, including internal designs. Speculation about the Exynos 2600 and next-generation Galaxy lineup has repeatedly surfaced as part of this story. Samsung is trying to prove 2nm not through technical demos but through actual products and customer wins.

On the customer pipeline side, a meaningful event has occurred. A reported long-term supply agreement with Tesla worth $16.5 billion gives Samsung Foundry a foundation for securing sustained volume and accelerated learning. Qualcomm, which appeared to have left, is showing signs of returning. A handful of purpose-built chip companies and AI startups are also reported to be evaluating Samsung’s process or being discussed as potential customers. Samsung’s aggressive pricing has been a consistent theme in the market, and the company appears intent on re-establishing itself as a credible alternative to TSMC.

Looking at all three players side by side, the roles become distinct. TSMC remains the benchmark. Intel is targeting specific high-performance segments with PowerVia as its differentiator. Samsung is trying to re-enter the consideration set by competing on price and supply optionality. For Intel, Samsung is both a lesson and a threat. The lesson is that technical leadership does not automatically translate into market leadership. The threat is that as Samsung recovers, the “alternative premium” Intel currently enjoys begins to erode.

The Narrowing Window of Opportunity

The “multi-sourcing” strategies of fabless customers are creating a structural opportunity for Intel. Apple, Nvidia, AMD, and Qualcomm all want to reduce their risk from single-source dependence on TSMC. GlobalFoundries has already stepped off the leading-edge treadmill. Rapidus in Japan is targeting 2nm but has no production track record, with volume manufacturing expected no earlier than 2027. By process of elimination, Intel looks like the only real alternative.

But that window is narrowing. Samsung is pushing SF2 yield higher while also preparing SF2P, and is beginning to register again as a genuine option. Samsung’s pricing competitiveness and the American production capacity at its Taylor fab directly undercut Intel’s differentiators. TSMC isn’t standing still, either. Its N4 fab in Arizona is in operation, JASM in Kumamoto, Japan is running, and a fab is under construction in Dresden, Germany. The geopolitical premium Intel derives from domestic U.S. production is being diluted with each passing quarter.

That makes 2026 and 2027 a time problem for Intel. If Intel cannot demonstrate, within that window, the production reproducibility and ecosystem depth that external customers require, those customers will either stay with the proven TSMC or turn toward a resurgent Samsung.

3. Intel’s Survival Strategy: Customers, Challenges, and Scenarios

The Customer Pipeline Taking Shape

Apple: The Name That Could Change Everything

Since late 2025, the hottest story in the industry has been the possibility of Apple becoming an Intel Foundry customer. According to analyst Ming-Chi Kuo, Apple has already received Intel’s 18A-P process PDK 0.9.1GA and is running internal simulations, with results reportedly meeting expectations. When PDK 1.0 arrives in Q1 2026, formal qualification is expected to begin in earnest.

The target products are entry-level M-series processors for the MacBook Air and iPad Pro, at an estimated annual volume of 15 to 20 million units. Starting with the lowest-tier chips rather than the Pro or Max line is realistic. From Apple’s perspective, it minimizes risk while validating Intel’s production capability, with room to expand volume incrementally if the results hold up. KeyBanc Capital Markets analyst John Vinh has gone further, indicating that Apple is in discussions about manufacturing entry-level iPhone A-series processors on Intel’s 14A process around 2029.

Apple’s motivation for considering Intel Foundry is straightforward. In the Q1 2026 earnings call, Tim Cook directly acknowledged supply constraints and expressed difficulty predicting when supply-demand balance would be restored. One hundred percent dependence on TSMC weakens Apple’s negotiating leverage and exposes it to geopolitical risk in the Taiwan Strait. The deal is not confirmed. The first half of 2026 will be the go/no-go inflection point.

Nvidia: A Cautious Approach, but a Meaningful Signal

Nvidia’s relationship with Intel is more complicated. In September 2025, Nvidia announced a $5 billion investment in Intel (completed in December, representing approximately 4% stake), with the two companies agreeing to collaborate on developing SoCs integrating x86 CPUs and Nvidia GPUs.

On the foundry side, signals have been mixed. Reuters reported that Nvidia tested Intel’s 18A process but “stopped moving forward,” with the interpretation being that yield and performance fell short of expectations. Nvidia had already secured TSMC N2 capacity for its next-generation 2nm-class designs, so the motivation for switching to Intel 18A was limited.

In January 2026, however, DigiTimes reversed the narrative. The report indicated that Nvidia is exploring manufacturing the I/O die for its next-generation GPU architecture, codenamed Feynman (expected around 2028), on Intel’s 18A or 14A process. The structure keeps the core GPU compute die with TSMC while assigning roughly 25% of I/O die work and advanced packaging via EMIB to Intel. This allows Nvidia to keep the most performance-sensitive compute die with a proven partner while using the I/O die as a lower-risk proving ground for Intel. It is a textbook foundry diversification strategy.

Microsoft and AWS: Anchor Customers Already in Motion

Beyond Apple and Nvidia, customers are already moving. Microsoft plans to produce Maia 2, its AI accelerator for Azure data centers, on Intel 18A. AWS is working with Intel on custom Xeon processors and AI fabric interconnect chips. The reason these hyperscalers are choosing Intel has less to do with technical superiority than with strategic diversification. With AI infrastructure demand exploding and TSMC’s advanced process capacity chronically constrained, securing alternative production capability on domestic U.S. soil is a rational supply chain resilience decision.

Five Thresholds Intel Must Clear

First: The yield inflection point in the first half of 2026. Before anything else, 18A process yield must reach a level sufficient to accept external customers. Volume production of Panther Lake (PC) and Clearwater Forest (server) needs to serve as the living proof of 18A’s maturity. No external customer will sign up for a process that can’t reliably produce Intel’s own chips.

Second: 18A-P must ship on time. If 18A is optimized for Intel’s own CPUs, 18A-P is the real foundry process. The timeline for PDK 1.0 and production ramp must align with the schedules of external customers, including Apple. In foundry, schedule slippage equals customer attrition.

Third: The real contest is 14A. Intel 18A is not the ideal process for most external foundry customers. The decisive battle shifts to 14A, expected around 2027, which would be the first commercial application of High-NA EUV lithography. If Intel can establish a genuine technical advantage over TSMC at that node, it could be a game changer. Intel has already declared, however, that it will not invest without customer commitments. The “build it and they will come” approach is no longer on the table.

Fourth: EMIB packaging as a side door. Intriguingly, the fastest path for Intel to attract foundry customers may not be wafer processing at all, but advanced packaging. Intel’s EMIB and Foveros technologies are best-in-class, and TSMC’s CoWoS packaging has been chronically supply-constrained under the surge in AI demand. The Nvidia Feynman deal is itself centered on EMIB. Packaging revenue may arrive ahead of wafer processing revenue, and it could be the foot-in-the-door that establishes relationships with foundry customers.

Fifth: Converting geopolitical tailwinds into execution. Taiwan Strait risk, $7.86 billion in direct CHIPS Act grants plus a separate government equity stake of approximately 9.9%, and U.S. Department of Defense demand for domestic production — all of these work structurally in Intel’s favor. But as TSMC Arizona ramps and Samsung Taylor comes online, this premium shrinks over time. Government subsidies can bridge early cost gaps, but Intel must independently build its technical competitiveness. The window is the period before TSMC Arizona and Samsung Taylor reach full capacity.

Two Scenarios

Bull Case: The Flywheel Starts Turning

PDK timelines hold. Internal product production proves process maturity. Apple and Nvidia commit meaningful volume. External customer inflows accelerate yield learning. 14A arrives on schedule, capturing the first-mover advantage of High-NA EUV. Foundry operating losses begin to shrink. By the end of the decade, Intel captures a meaningful share of the global foundry market.

Bear Case: The Window Closes

Process schedules slip. Production maturity disappoints. Apple defers its decision or limits engagement to a small pilot. Nvidia ultimately stays with TSMC. TSMC Arizona ramps and erodes the domestic-production premium. External customer volume fails to materialize. Large-scale losses persist. Investment in 14A is scaled back. Strategic retreat from the foundry business returns to the table.

Conclusion

Intel Foundry’s contest has moved past the stage of “potential” and into the stage of “proof.”

If 18A demonstrated the direction of the technology through internal products, 18A-P is the first gate through which external customers must decide whether to commit their trust and their tapeouts. If that gate is cleared and volume begins to flow, learning accelerates, the ecosystem follows, and 14A becomes the card that turns the game.

If that timing is missed, customers stay with the proven TSMC, the remaining alternatives are divided with Samsung, and Intel’s foundry strategy will once again face pressure to contract. Which scenario unfolds depends, in the end, on what Intel can execute from the inside.